Test R+dmb.st+rfi-addr-[fr-rf]-addr

AArch64 R+dmb.st+rfi-addr-[fr-rf]-addr
"DMB.STdWW Wse Rfi DpAddrdR FrLeave RfBack DpAddrdR Fre"
Cycle=Rfi DpAddrdR FrLeave RfBack DpAddrdR Fre DMB.STdWW Wse
Relax=
Safe=Rfi Fre Wse DMB.STdWW DpAddrdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr Rf
Orig=DMB.STdWW Wse Rfi DpAddrdR FrLeave RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X9=x;
2:X1=z;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | MOV W0,#2           | MOV W0,#1   ;
 STR W0,[X1] | STR W0,[X1]         | STR W0,[X1] ;
 DMB ST      | LDR W2,[X1]         |             ;
 MOV W2,#1   | EOR W3,W2,W2        |             ;
 STR W2,[X3] | LDR W4,[X5,W3,SXTW] |             ;
             | LDR W6,[X5]         |             ;
             | EOR W7,W6,W6        |             ;
             | LDR W8,[X9,W7,SXTW] |             ;
Observed
    z=1; y=2; x=1; 1:X8=1; 1:X6=0; 1:X4=1; 1:X2=2;
and z=1; y=1; x=1; 1:X8=1; 1:X6=0; 1:X4=1; 1:X2=2;
and z=1; y=2; x=1; 1:X8=0; 1:X6=0; 1:X4=1; 1:X2=2;
and z=1; y=1; x=1; 1:X8=0; 1:X6=0; 1:X4=1; 1:X2=2;
and z=1; y=1; x=1; 1:X8=1; 1:X6=0; 1:X4=1; 1:X2=1;
and z=1; y=1; x=1; 1:X8=0; 1:X6=0; 1:X4=1; 1:X2=1;